1. Field of the Invention
The present invention relates to the protection of integrated circuit pads against electrostatic discharges.
2. Discussion of the Related Art
As is known, an integrated circuit is connected to external circuits through input and output pads, which are in turn connected to pins. The internal components of integrated circuits are generally sensitive to electrostatic overvoltages that are capable of destroying them. Generally, each integrated circuit pad is connected to an electrostatic discharge protection circuit, a schematic example of which is illustrated in the drawing of FIG. 1.
FIG. 1 schematically shows a pad connected, by way of example, to the input gate of a MOS transistor. The integrated circuit is coupled between a high supply voltage VDD and a low supply voltage VSS, for example, ground. The pad is connected to the low and high voltage terminals through biased diodes D1 and D2, as shown in FIG. 1. Thus, if the pad becomes more negative than VSS (minus a forward diode voltage drop), the overvoltage passes through diode D1 and is absorbed by VSS. If the pad becomes more positive than VDD (plus a forward diode voltage drop), the overvoltage passes through diode D2 and is absorbed by VDD. In both cases, the device connected to the pad, for example a MOS transistor, is protected.
The invention is more particularly directed to a technology such as the one, for example, used for realizing bipolar and MOS (BICMOS) dual integrated circuits using a substrate of a first conductivity type coated with an epitaxial layer of the second conductivity type. Such technology comprises means to form, at the interface between the substrate and the epitaxial layer, N or P-type buried layers and means to form, in the epitaxial layer, pockets of the first conductivity type and, of course, various N or P-type doped regions in the pockets and in the substrate from the integrated circuit surface.
FIGS. 2 and 3 show conventional structures used in the prior art to fabricate diodes D1 and D2, respectively, of FIG. 1 when the substrate 1 is of the P-type and the epitaxial layer 2 is of the N-type.
FIG. 2 schematically shows a conventional implementation of diode D1 of FIG. 1. Diode D1 is formed in a P-type pocket 3 contacting by its lower surface a highly doped buried P-type layer 4. From the surface of the pocket are formed a first N-type region 6 and a second P-type region 7. Region 7 is, for example, an annular region surrounding region 6. Region 7, which electrically contacts substrate 1 through pocket 3 and buried layer 4, is necessarily polarized at the substrate voltage, that is, the low voltage VSS. Region 6 is connected to the pad. Thus, diode D1 is formed at the junction between pocket 3 and region 6 as shown in FIG. 2 Additionally, outside the pocket, is represented a portion 10 of the epitaxial layer 2 and an N.sup.+ -type ring formed by a buried layer 8 and a N.sup.+ -type deep diffusion 9; the upper surface of region 9 is covered by a metallization connected to the high voltage VDD. The ring formed by layer 8 and diffusion 9 is used for polarizing the portion 10 of the epitaxial layer which constitutes the collector of an NPN transistor whose emitter-base junction corresponds to diode D1 and that collects the charges transmitted when diode D1 is conductive.
Additionally, the structure is surrounded by a substrate contact, such as described hereinafter with reference to FIG. 3, for isolating the portion 10 of the epitaxial layer and the N.sup.+ -type ring 8-9.
FIG. 3 schematically shows an exemplary conventional implementation of diode D2 of FIG. 2. Diode D2 is formed in a portion 11 of the epitaxial layer 2 beneath which is formed an N+-type buried layer 12. An N.sup.+ -type diffused ring 13 contacts the buried layer 12 and insulates portion 11. A P.sup.+ -type region 14 is diffused in the portion of layer 11. Region 14 is connected to the pad and the upper surface of region 13 is connected to voltage VDD. Thus, diode D2 is formed at the junction between region 14 and the portion of N-type layer 11. At the periphery of the above-described structure is shown a substrate contact, that is, a P.sup.+ -type buried layer 15 contacted by a P-type diffusion 16 at the surface of which is formed a P.sup.+ -type diffused region 17 integral with a substrate polarization contact connected to voltage VSS. This substrate contact forms the collector of a PNP transistor whose emitterbase junction corresponds to diode D2 and which collects the charges transmitted when the diode is conductive.
FIG. 3 is shown separately from FIG. 2 although in practice the two diodes D1 and D2 are formed on a single integrated circuit and can be adjacent.